Memory integrated circuits “ICs” for use with most computers operate at speeds slower than current generation central processing unit “CPU” ICs creating a condition generally referred to as the “memory bottleneck”. In such condition, the CPU must remain in a wait state until the memory data is written or retrieved. The problem has been addressed, in part, by improved memory system designs. However as electronic systems move into the multi-gigabit per second data rate range, a significant gap remains between top-end operating rates of CPU ICs and memory ICs. Part of this ongoing disparity is due to the limits of current interconnection design, which often results, particularly at higher frequencies, in disturbances that contribute to signal distortion. For example, signal distortion can often be due, at least in part to so-called parasitic effects resulting from traditional interconnect designs. Because signal speed and signal integrity are two primary goals in digital signal transmission, interconnect designs that assure signal integrity during data transmission are key. Controlling signal integrity begins with the design of the circuit. Choices made in terms of circuit layout, and the materials used and the general architecture of the complete assembly, will all have impact of the quality if the signal transmission and its ultimate integrity.
Because parasitic effects and signal discontinuity are primary sources of signal disturbance, one of the major objectives in maintaining signal integrity is to eliminate or minimize the parasitic effects and electrical discontinuities impinging upon a signal. Parasitic effects and electrical discontinuities are caused by a number of factors such as sharp changes in direction, changes in material, circuit feature flaws and even interconnections, such as solder balls used to connect IC packages to next level interconnection substrates. All these can affect signal integrity by introducing undesirable changes in impedance and creating signal reflections. There is also concern about signal skew, cause by differing signal lengths, which is important in assuring proper signal timing.
The first place in an electronic system such parasitic effects are encountered, beyond those encountered within the IC structure itself, is the IC package which is used to connect the IC die to a next level interconnection system. While current generation IC packages are presently reasonably well suited to meeting current needs, as the electronics industry moving to ever higher data signaling rates, the formerly minor concerns associated with packages and interconnection paths have now reached a level of critical importance.
The net effect of this complex web of interactive elements is that they collectively combine to make it extremely difficult to predict and design for reliable high performance at higher processing speeds. Additionally, at higher processing speeds, parasitic effects and signal discontinuities and reflections can contribute to the thermal demands placed on a system. Thus, as memory circuit speeds climb, there is need for new approaches to design of memory package interconnections to overcome the looming and highly complex electrical and thermal problems associated with traditional approaches to IC memory packaging.